Course name: UVM

Code: UVM

Training content

Day 1 – SystemVerilog for Verification

• Verification Overview and Introduction to SystemVerilog, Data types, operators and Literals
• Procedural and control statements

Day 2: SystemVerilog for Verification

• Subroutines, Interfaces, Arrays and Queues, Object oriented Design/Verification, TLM Level Modeling

Day 3: SystemVerilog for Verification

• Randomization, Classes, Coverage and cover group, CPF/UPF for power island simulation,
• Coding rule checkers

Day 4: Assertion Based Verification

• SV-Assertions, SVA checker library, Property checkers, Sequences, Advanced SVA constructs, Assertion Coverage, OVL

Day 5: UVM (Universal Verification Methodology)

• UVM, Assertions in UVM.

Training purpose

• Students learn and practice with UVM to be able to build their own testbench for verification based on UVM.

References

• A Practical Guide to Adopting Universal Verification Methodology (UVM)