Trainer
Dr. Le Thai Ha
Students
30
Duration
4 months
Certificate
Yes
Lectures
16 hours
Labs & HW
32 hours
Course name: System Verilog
Code: SV
Training content
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Introduction, Classification of HDLs
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Combinational Circuits Modeling
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Latches
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Registers
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Finite State Machine
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SystemVerilog as a Verification Language
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Environment
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Operators and Datatypes
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OOP
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Abstract Class
-
Thread
-
Events
-
Semaphore
-
Mailbox
-
Environment
-
Covergroup, Coverpoint
Training purpose
- Provides basic to advanced HDL programming skills.
- Students can program, simulate and evaluate Chip blocks and modules themselves.
References
- Digital Integrated Circuits: A Design Perspective
- Introduction to Logic Circuits & Logic Design with Verilog
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