Trainer
Dr. Le Thai Ha
Students
30
Duration
3 months
Certificate
Yes
Lectures
20 hours
Labs & HW
20 hours
Course name: IC Design Flow
Code: ICF
Training content
- Synopsys Design Flow – 2 lectures
- Logic Simulation (VCS) – 2 lectures
- Logic Synthesis (Design Compiler) – 2 lectures
- Physical Synthesis (IC Compiler II) – 2 lectures
- Static Timing Analysis (PrimeTime) – 2 lectures
- Formal Verification (Formality) – 2 lectures
- Automatic Test Pattern Generation (TetraMAX) – 2 lectures
- Physical Verification (IC Validator) – 2 lectures
- Layout Parasitics Extraction (StarRC) – 2 lectures
- SPICE-Level Simulation of Completed Design (HSpice) – 2 lectures
Training purpose
- Understanding and experience of complete Chip design cycle including Frontend, middle-end and backend.
References
- Digital Integrated Circuits: A Design Perspective
- Static Timing Analysis for Nanometer Designs: A Practical Approach
- VLSI Physical Design Automation – Theory and Practice
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