Trainer

Dr. Le Thai Ha

Students

30

Duration

4 months

Certificate

Yes

Lectures

29 hours

Labs & HW

29 hours

Course name: IC Synthesis and Optimization

Code: ICS

Training content

Logic Synthesis – 2 lectures
Timing and Area Constraints – 2 lectures
Attributes and Constraints – 5 lectures
Introduction to Synthesis Design Constraint (SDC) – 1 lectures
Introduction to scripting languages (Perl & tcl) – 6 lectures
Synthesis Design Constraint (SDC) with Scripting Languages – 4 lectures
Compile Strategies – 5 lectures
Physical Design Introduction (Floorplanning, CTS, PnR, OCV, Power Optimization, PV, Power Estimation) – 4 lectures

Training purpose

General and practical knowledge of Synthesis and the entire cycle from Logic Synthesis to GDS.

References

Digital Integrated Circuits: A Design Perspective
Digital Integrated Circuits: A Design Perspective
Static Timing Analysis for Nanometer Designs: A Practical Approach

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