Trainer
Dr. Le Thai Ha
Students
30
Duration
4 months
Certificate
Yes
Lectures
7 hours
Labs & HW
20 hours
Course name: Verification for Low power design
Code: VLPD
Training content
- Low power design introduction – 1 lecture
- Impact of LPD on Digital design – 1 lecture
- Power management bugs – 3 lectures
- VMM-LP Class Library – 2 lectures
Training purpose
- Students can understand the important steps in the process of verifying low-power chip designs.
References
- Verification Methodology Manual for Low Power
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