Course name: System Verilog

Code: SV

Training content

• Introduction, Classification of HDLs
• Combinational Circuits Modeling
• Latches
• Registers
• Finite State Machine
• SystemVerilog as a Verification Language
• Environment
• Operators and Datatypes
• OOP
• Abstract Class
• Thread
• Events
• Semaphore
• Mailbox
• Environment
• Covergroup, Coverpoint

Training purpose

• Provides basic to advanced HDL programming skills.
• Students can program, simulate and evaluate Chip blocks and modules themselves.

References

• Digital Integrated Circuits: A Design Perspective
• Introduction to Logic Circuits & Logic Design with Verilog