Trainer
Dr. Le Thai Ha
Students
30
Duration
4 months
Certificate
Yes
Lectures
50 hours
Labs & HW
75 hours
Course name: Design For Test
Code: DFT
Training content
Topic 1 – Introduction
Verification vs. Testing, Need for testing, Level of testing, Cost of testing, Roles of testing.
Topic 2 – Test Process and Equipment
Types of testing, Manufacturing test, Burn-in and stress test, Functional test, Automatic test equipment (ATE), Electrical parameter testing, DC parameter testing, AC parameter test.
Topic 3 – Test Economics
Basics of cost analysis, Benefit-cost analysis, Economics of design-for-testability (DFT), VLSI chip yield, Defect level.
Topic 4 – Logic and Fault Modeling
Logic modeling, Model types, Models at different levels of abstractions, Fault modeling, Common fault models, Stuck-at-faults, Transistor (switch) faults.
Topic 5 – Fault Simulation
Usage of fault simulators, Fault simulator in a VLSI design process, Fault simulation algorithms: Serial, Parallel, Deductive, Concurrent, Fault sampling.
Topic 6 – Combinational ATPG (I)
Structural vs. functional test, Definition of ATPG, Exhaustive algorithm, Random pattern generation, Boolean difference symbolic method, Path sensitization method, Computation complexity.
Topic 7 – Combinational ATPG (II)
Major ATPG algorithms, D-Algorithm, PODEM.
Topic 8 – ATPG Systems and Testability Measures
ATPG systems, Static and dynamic compaction, Fault coverage and efficiency, Testability analysis, SCOAP measures, Controllability measure, Observability measure.
Topic 9 – Sequential Circuit ATPG
Time frame expansion, Nine-valued logic, Drivability, Complexity of ATPG, Test generation system.
Topic 10 – Functional Testing
Structure independent approach, Structure dependent approach, Microprocessor testing.
Topic 11 – Delay Test
Path delay fault testing, transition fault testing, pattern generation, Scan-based delay fault test.
Topic 12 – Design-for-Testability (DFT) (I)
Definition, Ad-hoc DFT methods, Scan design, Scan flip-flop, Muxed-DFF, LSSD, Scan test vectors, Multiple scan registers, Hierarchical scan.
Topic 13 – Design-for-Testability (DFT) (II)
Partial scan architecture, Scan flip-flop selection methods, Cyclic and acyclic structures, Scan-hold flip-flops.
Topic 14 – IDDQ Current Testing
History and motivation, Basic principle of IDDQ testing, Fault detected by IDDQ tests, Limitations of IDDQ testing.
Topic 15 – Memory Testing
Motivation, Functional model of a memory, Fault models, March tests
Topic 16 – Built-In Self-Test (BIST) (I)
Motivation, BIST definitions, BIST process, BIST pattern generation, BIST response compaction, Aliasing definition.
Topic 17 – Built-In Self-Test (BIST) (II)
Motivation, Built-in logic block observer, Test/clock systems, Test/scan systems, Test point insertion
Training purpose
- Understanding and experience of complete Chip design cycle including Frontend, middle-end and backend.
References
- Digital Integrated Circuits: A Design Perspective
- Static Timing Analysis for Nanometer Designs: A Practical Approach
- VLSI Physical Design Automation – Theory and Practice
Register now
Full name
Phone
Course category
Courses
✔
{{ course }}
Message
CONGRATULATIONS!
You have successfully registered! We will contact you as soon as we have class information!