Trainer
Dr. Le Thai Ha
Students
30
Duration
4 months
Certificate
Yes
Lectures
34 hours
Labs & HW
34 hours
Course name: Advanced Methods in Logic Synthesis and Equivalence Checking
Code: LSEC
Training content
- Logic Synthesis – 2 lectures
- Timing and Area Constraints – 2 lectures
- Attributes and Constraints – 5 lectures
- Introduction to Synthesis Design Constraint (SDC) – 1 lecture
- Synthesis Design Constraint (SDC) with Scripting Languages – 4 lectures
- Compile Strategies – 5 lectures
- Logic Synthesis Problem – 1 lecture
- Logic Optimization – 1 lecture
- Logic Design Components – 3 lectures
- Advanced Methods in Synthesis – 5 lectures
- Combinational and Sequential Equivalent Checking – 5 lectures
Training purpose
- Students can Synthesis at a basic level and progress to a more advanced level with optimal steps. Students can conduct equivalence checks..
References
- Static Timing Analysis for Nanometer Designs: A Practical Approach 2009th Edition
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