Trainer

Dr. Le Thai Ha

Students

30

Duration

4 months

Certificate

Yes

Lectures

22 hours

Labs & HW

22 hours

Course name: Soft IP Development Flow

Code: SIP

Training content

Introduction to Soft IP Development Process – 2 lectures
Overview of Logic Design – 2 lectures
Verilog HDL and Digital Design Flow – 2 lectures
Design Tool Checks – 2 lectures
Introduction to Verification – 2 lectures
System Verilog Test Environment – 2 lectures
System Verilog and OOP Basics – 2 lectures
System Verilog Functional Coverage – 2 lectures
Soft IP FPGA Validation – Introduction to FPGA design – 2 lectures
Soft IP FPGA Validation – FPGA Structure and Design Flow – 2 lectures
Soft IP Packaging and Component Verification – 2 lectures

Training purpose

Students fully understand the Soft IP development cycle for Chip and FPGA.

References

Digital Integrated Circuits: A Design Perspective
Static Timing Analysis for Nanometer Designs: A Practical Approach
VLSI Physical Design Automation – Theory and Practice

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